Abstract: The principles and design of a pipelined processor architecture for parallel interpretation of high-level machine languages is presented. A new instruction encoding method, that facilitates the design of pipelines, is used to design the instruction sets of the controller, memory, and execution units. Performance profiles of seven benchmark programs, obtained by using a cycle-level simulator, show the speedup of about two relative to equivalent processor for serial interpretation.
Key words: Pipelined processor architecture, high level machine languages, minimally synchronized architecture.