Abstract: This paper is related to the experimental design of the RCA's 32-bit GaAs microprocessor on a single VLSI chip. The baseline architecture for this design was a Stanford University MIPS like machine which implements a software mechanism for the control of sequencing hazards. The RCA's GaAs architecture implements the same mechanism, but enhanced through the incorporation of the "ignore" instruction. This paper tries to provide an answer on how much does the incorporation of the "ignore" instruction speed up the execution of the compiled HLL code. The approach based on the "ignore" instruction is compared with both the SU-MIPS and the MIPS-X approaches to the problem, using both benchmarking and tracing.
Key words: Microprocessor, VLSi chip, microprocessor architecture