Abstract: This paper presents a method for the extraction of integrated circuit critical areas based on a transformation of CIF files from the unrestricted to a restricted format and a local layout extraction approach. The restricted format contains a set of non-overlapping rectangles that abut only along horizontal edges. The extraction of integrated circuit critical areas associated with short and open circuits is carried out by an algorithm that solves this problem time proportional to nsqrt{n}, on average, where n is the total number of the analyzed geometrical objects (rectangles). This algorithm is a typical scanline algorithm with singly-linked lists for storing and sorting the incoming objects. The performance of our method is illustrated on five layout examples by the analysis of CPU time consumed for computing the critical areas applying a software tool system TRACIF/EXACCA/GRAPH.
Key words: Lithography, yield, integrated circuits, layout.