We focus our attention on convolution of time discrete and digital signals, as one of many compute--bound problems that can benifit from systolic approach. H.T. Kung in [1] presents a family of semi--systolic (B1, B2 and F) and pure--systolic designs for the convolution problem. The semi--systolic architecture of type F is used as a basic structure for synthesis of the digit--serial convolver described in this paper. With a goal to transform this architecture into a digit--serial one, it was necessary to modify it. In essence, the proposeded modification primary relates to involving digit--serial processing elements (PEs) for multiplication and addition, instead of bit--parallel, as basic constituents of the convolver. The modified structure is characterized by the digit--serial processing in pipeline fashion, the reduced size of hardware in respect to the bit parallel version, and the feeding of input data without dummy values, i.e. PEs are fully utilized. Digit--serial PEs are implemented in LSD-frst (Least Significant Digit) integer arithmetic with the two's complement number representation.